Regarding Ethernet or 10GBASE-T, from 2017 [10GBASE-T is finally popular?], We delivered a total of 11 times and 2 extra editions.However, Ethernet for copper wiring by twisted pair is up to 10GBASE-T, and 25 / 40GBASE-T has not yet been put into practical use.At the May 2021 meeting, several other proposals were made regarding the electrical layer, such as "Electrical Interface Objective Wording" and "Considerations on beyond 100G per lane electrical objectives."On the other hand, by using LNoI (Lithium Niobate on Insulator: optical waveguide device using lithium niobate) as "LN-on-Insulator Modulator Technology for B400G Ethernet Application" from Huawei, promising results can be obtained with 200G PAM4. A simple survey result that can be obtained was also shown.As a result, Objective was revised at the following July meeting, and it was laughable that the "stupid solution" using OSFP-XD, which I mentioned a little at the end of the last time, was immediately proposed.Proponents are Paul Brooks of VIAVI solutions and Xinyuan Wang of Huawei.Their suggestion is that adding 100G x 16 to the AUI interface will speed up standardization.In the past history, it is normal for one Ethernet standard to include multiple AUI options, for example 800G has 100G x 8 and 200G x 4, so 1.6T is 100G x 16 and 200G. It should be okay to have x8.In the first place, it is estimated from 2026 to 2027 when it will be possible to realize 200G lane for AUI from the past CMOS roadmap.He argues that even if it eventually moves to 200G, it's okay to connect with 100G lanes in the meantime.Of course, it would take an extra year or two to start an ASIC here, but in the case of test equipment and first-generation products, FPGA-based development is not uncommon, and this is Tape out (physical placement). After the design including wiring is completed), it will be put into mass production immediately.The problem is that the FPGA will be well ahead of the 200G.In the sense of this kind of advanced product, it will be Xilinx's "Virtex / Versal" series and Intel (formerly Altera) "Stratix / Agilex" series, but the current situation is whether it is Xilinx's Versal Premium or Intel's Agilex. The installed general-purpose high-speed SerDes has a maximum speed of 58G (112G for PAM4, 116G for Agilex) in NRZ, and there is no product that supports 200G.This leads to the early launch of 1.6T Ethernet, which is not a bad story.So, I ended the presentation with a proposal to add a 16-lane configuration to the 1.6Tb / s Ethernet AUI, but this is just the AUI, that is, the specifications of the device and module (or inside the module). The optical interface is not considered.Given the current 200Gb / s x 8 lane configuration, you'll have to put a 2: 1 Gearbox inside the module.What about that Gearbox instrument?It seems to be a story.Including that, I can understand what I'm saying, but I can't help but feel that it's a "stupid solution."No, if the specifications such as SMF x 16 are decided according to this, that is the way to go.Free technical writer.We have a wide range of fields of expertise, from CPUs, memories and chipsets to communication-related, OS, databases, and medical-related fields.The homepage is http://www.yusuke-ohara.com/Facebook and Microsoft DC operators preceded 400GbE, Beyond 400G Study Group insists on standardization of 1.6T at the same time as 800GMaintaining MTTFPA of 1.0E10 years, 1.0E-14 BER Target requires high cost FECOTN support for Beyond 400 Gb / s Ethernet was rejected by vote in AprilCopyright © 2018 Impress Corporation. All rights reserved.